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Reduce code duplication

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This commit is contained in:
Werner
2021-11-19 19:59:05 -03:00
parent ae70b9db3d
commit 03e43f39ce
4 changed files with 193 additions and 216 deletions
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370
Source/Instructions.rs
View File

@ -1,4 +1,5 @@
use crate::Machine; use crate::Payload::{ThreeRegisters, TwoRegisters};
use crate::{Machine, Payload};
pub fn Nothing(vm: &mut Machine) -> bool { pub fn Nothing(vm: &mut Machine) -> bool {
vm.Next(); vm.Next();
@ -6,22 +7,22 @@ pub fn Nothing(vm: &mut Machine) -> bool {
} }
pub fn LoadRegister(vm: &mut Machine) -> bool { pub fn LoadRegister(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let (reg, addr) = Payload::GetRegisterAddress(vm);
let addr = vm.ReadWord(None);
let val = vm.ReadWord(Some(addr));
vm.registry.Set(reg, val); let data = vm.ReadWord(Some(addr));
vm.registry.Set(reg, data);
vm.Walk(5); vm.Walk(5);
true true
} }
pub fn SaveRegister(vm: &mut Machine) -> bool { pub fn SaveRegister(vm: &mut Machine) -> bool {
let addr = vm.ReadWord(None); let (addr, reg) = Payload::GetAddressRegister(vm);
let reg = vm.ReadByte(None);
let val = vm.registry.Get(reg);
vm.WriteWord(Some(addr), val); let data = vm.registry.Get(reg);
vm.WriteWord(Some(addr), data);
vm.Walk(5); vm.Walk(5);
true true
@ -33,131 +34,106 @@ pub fn Move(_vm: &mut Machine) -> bool {
} }
pub fn Add(vm: &mut Machine) -> bool { pub fn Add(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let payload = Payload::GetThreeRegisters(vm);
_Add(vm, payload)
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, (op1 + op2).to_be_bytes());
vm.Walk(3);
true
} }
pub fn AddAssign(vm: &mut Machine) -> bool { pub fn AddAssign(vm: &mut Machine) -> bool {
let reg1 = vm.ReadByte(None); let payload = Payload::GetTwoRegisters(vm);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); _Add(vm, (payload.0, payload.0, payload.1))
let reg2 = vm.ReadByte(None); }
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg1, (op1 + op2).to_be_bytes()); #[inline]
vm.Walk(2); fn _Add(vm: &mut Machine, payload: ThreeRegisters) -> bool {
let a = u32::from_be_bytes(vm.registry.Get(payload.1));
let b = u32::from_be_bytes(vm.registry.Get(payload.2));
vm.registry.Set(payload.0, (a + b).to_be_bytes());
vm.Walk(3);
true true
} }
pub fn Subtract(vm: &mut Machine) -> bool { pub fn Subtract(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let payload = Payload::GetThreeRegisters(vm);
_Subtract(vm, payload)
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, (op1 - op2).to_be_bytes());
vm.Walk(3);
true
} }
pub fn SubtractAssign(vm: &mut Machine) -> bool { pub fn SubtractAssign(vm: &mut Machine) -> bool {
let reg1 = vm.ReadByte(None); let payload = Payload::GetTwoRegisters(vm);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); _Subtract(vm, (payload.0, payload.0, payload.1))
let reg2 = vm.ReadByte(None); }
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg1, (op1 - op2).to_be_bytes()); #[inline]
vm.Walk(2); fn _Subtract(vm: &mut Machine, payload: ThreeRegisters) -> bool {
let a = u32::from_be_bytes(vm.registry.Get(payload.1));
let b = u32::from_be_bytes(vm.registry.Get(payload.2));
vm.registry.Set(payload.0, (a - b).to_be_bytes());
vm.Walk(3);
true true
} }
pub fn Multiply(vm: &mut Machine) -> bool { pub fn Multiply(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let payload = Payload::GetThreeRegisters(vm);
_Multiply(vm, payload)
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, (op1 * op2).to_be_bytes());
vm.Walk(3);
true
} }
pub fn MultiplyAssign(vm: &mut Machine) -> bool { pub fn MultiplyAssign(vm: &mut Machine) -> bool {
let reg1 = vm.ReadByte(None); let payload = Payload::GetTwoRegisters(vm);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); _Multiply(vm, (payload.0, payload.0, payload.1))
let reg2 = vm.ReadByte(None); }
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg1, (op1 * op2).to_be_bytes()); #[inline]
vm.Walk(2); fn _Multiply(vm: &mut Machine, payload: ThreeRegisters) -> bool {
let a = u32::from_be_bytes(vm.registry.Get(payload.1));
let b = u32::from_be_bytes(vm.registry.Get(payload.2));
vm.registry.Set(payload.0, (a * b).to_be_bytes());
vm.Walk(3);
true true
} }
pub fn Divide(vm: &mut Machine) -> bool { pub fn Divide(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let payload = Payload::GetThreeRegisters(vm);
_Divide(vm, payload)
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, (op1 / op2).to_be_bytes());
vm.Walk(3);
true
} }
pub fn DivideAssign(vm: &mut Machine) -> bool { pub fn DivideAssign(vm: &mut Machine) -> bool {
let reg1 = vm.ReadByte(None); let payload = Payload::GetTwoRegisters(vm);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); _Divide(vm, (payload.0, payload.0, payload.1))
let reg2 = vm.ReadByte(None); }
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg1, (op1 / op2).to_be_bytes()); #[inline]
vm.Walk(2); fn _Divide(vm: &mut Machine, payload: ThreeRegisters) -> bool {
let a = u32::from_be_bytes(vm.registry.Get(payload.1));
let b = u32::from_be_bytes(vm.registry.Get(payload.2));
vm.registry.Set(payload.0, (a * b).to_be_bytes());
vm.Walk(3);
true true
} }
pub fn Remainder(vm: &mut Machine) -> bool { pub fn Remainder(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let payload = Payload::GetThreeRegisters(vm);
_Remainder(vm, payload)
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, (op1 % op2).to_be_bytes());
vm.Walk(3);
true
} }
pub fn RemainderAssign(vm: &mut Machine) -> bool { pub fn RemainderAssign(vm: &mut Machine) -> bool {
let reg1 = vm.ReadByte(None); let payload = Payload::GetTwoRegisters(vm);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); _Remainder(vm, (payload.0, payload.0, payload.1))
let reg2 = vm.ReadByte(None); }
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg1, (op1 % op2).to_be_bytes()); #[inline]
vm.Walk(2); fn _Remainder(vm: &mut Machine, payload: ThreeRegisters) -> bool {
let a = u32::from_be_bytes(vm.registry.Get(payload.1));
let b = u32::from_be_bytes(vm.registry.Get(payload.2));
vm.registry.Set(payload.0, (a * b).to_be_bytes());
vm.Walk(3);
true true
} }
@ -168,216 +144,186 @@ pub fn Neg(_vm: &mut Machine) -> bool {
} }
pub fn And(vm: &mut Machine) -> bool { pub fn And(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let payload = Payload::GetThreeRegisters(vm);
_And(vm, payload)
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, (op1 & op2).to_be_bytes());
vm.Walk(3);
true
} }
pub fn AndAssign(vm: &mut Machine) -> bool { pub fn AndAssign(vm: &mut Machine) -> bool {
let reg1 = vm.ReadByte(None); let payload = Payload::GetTwoRegisters(vm);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); _And(vm, (payload.0, payload.0, payload.1))
let reg2 = vm.ReadByte(None); }
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg1, (op1 & op2).to_be_bytes()); #[inline]
vm.Walk(2); fn _And(vm: &mut Machine, payload: ThreeRegisters) -> bool {
let a = u32::from_be_bytes(vm.registry.Get(payload.1));
let b = u32::from_be_bytes(vm.registry.Get(payload.2));
vm.registry.Set(payload.0, (a & b).to_be_bytes());
vm.Walk(3);
true true
} }
pub fn Or(vm: &mut Machine) -> bool { pub fn Or(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let payload = Payload::GetThreeRegisters(vm);
_Or(vm, payload)
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, (op1 | op2).to_be_bytes());
vm.Walk(3);
true
} }
pub fn OrAssign(vm: &mut Machine) -> bool { pub fn OrAssign(vm: &mut Machine) -> bool {
let reg1 = vm.ReadByte(None); let payload = Payload::GetTwoRegisters(vm);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); _Or(vm, (payload.0, payload.0, payload.1))
let reg2 = vm.ReadByte(None); }
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg1, (op1 | op2).to_be_bytes()); #[inline]
vm.Walk(2); fn _Or(vm: &mut Machine, payload: ThreeRegisters) -> bool {
let a = u32::from_be_bytes(vm.registry.Get(payload.1));
let b = u32::from_be_bytes(vm.registry.Get(payload.2));
vm.registry.Set(payload.0, (a | b).to_be_bytes());
vm.Walk(3);
true true
} }
pub fn Xor(vm: &mut Machine) -> bool { pub fn Xor(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let payload = Payload::GetThreeRegisters(vm);
_Xor(vm, payload)
}
let reg1 = vm.ReadByte(None); pub fn XorAssign(vm: &mut Machine) -> bool {
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); let payload = Payload::GetTwoRegisters(vm);
let reg2 = vm.ReadByte(None); _Xor(vm, (payload.0, payload.0, payload.1))
let op2 = u32::from_be_bytes(vm.registry.Get(reg2)); }
vm.registry.Set(reg, (op1 ^ op2).to_be_bytes()); #[inline]
fn _Xor(vm: &mut Machine, payload: ThreeRegisters) -> bool {
let a = u32::from_be_bytes(vm.registry.Get(payload.1));
let b = u32::from_be_bytes(vm.registry.Get(payload.2));
vm.registry.Set(payload.0, (a ^ b).to_be_bytes());
vm.Walk(3); vm.Walk(3);
true true
} }
pub fn XorAssign(vm: &mut Machine) -> bool {
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg1, (op1 ^ op2).to_be_bytes());
vm.Walk(2);
true
}
pub fn Not(vm: &mut Machine) -> bool { pub fn Not(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let r0 = Payload::GetRegister(vm);
let op = u32::from_be_bytes(vm.registry.Get(reg));
vm.registry.Set(reg, (!op).to_be_bytes()); let a = u32::from_be_bytes(vm.registry.Get(r0));
vm.registry.Set(r0, (!a).to_be_bytes());
vm.Walk(2); vm.Walk(2);
true true
} }
pub fn ShiftLeft(vm: &mut Machine) -> bool { pub fn ShiftLeft(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let payload = Payload::GetTwoRegisters(vm);
_ShiftLeft(vm, payload)
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
vm.registry.Set(reg, (op1 << 1).to_be_bytes());
vm.Walk(3);
true
} }
pub fn ShiftLeftAssign(vm: &mut Machine) -> bool { pub fn ShiftLeftAssign(vm: &mut Machine) -> bool {
let reg1 = vm.ReadByte(None); let payload = Payload::GetRegister(vm);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); _ShiftLeft(vm, (payload, payload))
}
vm.registry.Set(reg1, (op1 << 1).to_be_bytes()); #[inline]
vm.Walk(2); fn _ShiftLeft(vm: &mut Machine, payload: TwoRegisters) -> bool {
let a = u32::from_be_bytes(vm.registry.Get(payload.1));
vm.registry.Set(payload.0, (a << 1).to_be_bytes());
vm.Walk(3);
true true
} }
pub fn ShiftRight(vm: &mut Machine) -> bool { pub fn ShiftRight(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let payload = Payload::GetTwoRegisters(vm);
_ShiftRight(vm, payload)
}
let reg1 = vm.ReadByte(None); pub fn ShiftRightAssign(vm: &mut Machine) -> bool {
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); let payload = Payload::GetRegister(vm);
_ShiftRight(vm, (payload, payload))
}
vm.registry.Set(reg, (op1 >> 1).to_be_bytes()); #[inline]
fn _ShiftRight(vm: &mut Machine, payload: TwoRegisters) -> bool {
let a = u32::from_be_bytes(vm.registry.Get(payload.1));
vm.registry.Set(payload.0, (a >> 1).to_be_bytes());
vm.Walk(3); vm.Walk(3);
true true
} }
pub fn ShiftRightAssign(vm: &mut Machine) -> bool {
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
vm.registry.Set(reg1, (op1 >> 1).to_be_bytes());
vm.Walk(2);
true
}
pub fn Equals(vm: &mut Machine) -> bool { pub fn Equals(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
let reg1 = vm.ReadByte(None); let a = u32::from_be_bytes(vm.registry.Get(r1));
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); let b = u32::from_be_bytes(vm.registry.Get(r2));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, ((op1 == op2) as u32).to_be_bytes()); vm.registry.Set(r0, ((a == b) as u32).to_be_bytes());
vm.Walk(3); vm.Walk(3);
true true
} }
pub fn NotEquals(vm: &mut Machine) -> bool { pub fn NotEquals(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
let reg1 = vm.ReadByte(None); let a = u32::from_be_bytes(vm.registry.Get(r1));
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); let b = u32::from_be_bytes(vm.registry.Get(r2));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, ((op1 != op2) as u32).to_be_bytes()); vm.registry.Set(r0, ((a != b) as u32).to_be_bytes());
vm.Walk(3); vm.Walk(3);
true true
} }
pub fn LessThan(vm: &mut Machine) -> bool { pub fn LessThan(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
let reg1 = vm.ReadByte(None); let a = u32::from_be_bytes(vm.registry.Get(r1));
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); let b = u32::from_be_bytes(vm.registry.Get(r2));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, ((op1 < op2) as u32).to_be_bytes()); vm.registry.Set(r0, ((a < b) as u32).to_be_bytes());
vm.Walk(3); vm.Walk(3);
true true
} }
pub fn LessEquals(vm: &mut Machine) -> bool { pub fn LessEquals(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
let reg1 = vm.ReadByte(None); let a = u32::from_be_bytes(vm.registry.Get(r1));
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); let b = u32::from_be_bytes(vm.registry.Get(r2));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, ((op1 <= op2) as u32).to_be_bytes()); vm.registry.Set(r0, ((a <= b) as u32).to_be_bytes());
vm.Walk(3); vm.Walk(3);
true true
} }
pub fn GreaterThan(vm: &mut Machine) -> bool { pub fn GreaterThan(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
let reg1 = vm.ReadByte(None); let a = u32::from_be_bytes(vm.registry.Get(r1));
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); let b = u32::from_be_bytes(vm.registry.Get(r2));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, ((op1 > op2) as u32).to_be_bytes()); vm.registry.Set(r0, ((a > b) as u32).to_be_bytes());
vm.Walk(3); vm.Walk(3);
true true
} }
pub fn GreaterEquals(vm: &mut Machine) -> bool { pub fn GreaterEquals(vm: &mut Machine) -> bool {
let reg = vm.ReadByte(None); let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
let reg1 = vm.ReadByte(None); let a = u32::from_be_bytes(vm.registry.Get(r1));
let op1 = u32::from_be_bytes(vm.registry.Get(reg1)); let b = u32::from_be_bytes(vm.registry.Get(r2));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.registry.Set(reg, ((op1 >= op2) as u32).to_be_bytes()); vm.registry.Set(r0, ((a >= b) as u32).to_be_bytes());
vm.Walk(3); vm.Walk(3);
true true

33
Source/Payload.rs Normal file
View File

@ -0,0 +1,33 @@
use crate::Machine;
use crate::Types::{Byte, Word};
pub type RegisterAddress = (Byte, Word);
pub type AddressRegister = (Word, Byte);
pub type Register = Byte;
pub type TwoRegisters = (Byte, Byte);
pub type ThreeRegisters = (Byte, Byte, Byte);
#[inline]
pub fn GetRegisterAddress(vm: &mut Machine) -> RegisterAddress {
(vm.ReadByte(None), vm.ReadWord(None))
}
#[inline]
pub fn GetAddressRegister(vm: &mut Machine) -> AddressRegister {
(vm.ReadWord(None), vm.ReadByte(None))
}
#[inline]
pub fn GetRegister(vm: &mut Machine) -> Register {
vm.ReadByte(None)
}
#[inline]
pub fn GetTwoRegisters(vm: &mut Machine) -> TwoRegisters {
(vm.ReadByte(None), vm.ReadByte(None))
}
#[inline]
pub fn GetThreeRegisters(vm: &mut Machine) -> ThreeRegisters {
(vm.ReadByte(None), vm.ReadByte(None), vm.ReadByte(None))
}

5
Source/Types.rs
View File

@ -1,5 +1,2 @@
/// Canonical byte type.
pub type Byte = u8; pub type Byte = u8;
pub type Word = [Byte; 4];
/// Canonical data and address type.
pub type Word = [u8; 4];

1
Source/lib.rs
View File

@ -3,6 +3,7 @@
mod Instructions; mod Instructions;
pub mod Operations; pub mod Operations;
pub mod Payload;
pub mod Types; pub mod Types;
#[path = "Limits.rs"] #[path = "Limits.rs"]