mirror of
https://github.com/guilhermewerner/machine
synced 2025-06-15 20:54:20 +00:00
Reduce code duplication
This commit is contained in:
Werner
@ -1,4 +1,5 @@
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use crate::Machine;
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use crate::Payload::{ThreeRegisters, TwoRegisters};
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use crate::{Machine, Payload};
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pub fn Nothing(vm: &mut Machine) -> bool {
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vm.Next();
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@ -6,22 +7,22 @@ pub fn Nothing(vm: &mut Machine) -> bool {
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}
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pub fn LoadRegister(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let addr = vm.ReadWord(None);
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let val = vm.ReadWord(Some(addr));
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let (reg, addr) = Payload::GetRegisterAddress(vm);
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vm.registry.Set(reg, val);
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let data = vm.ReadWord(Some(addr));
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vm.registry.Set(reg, data);
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vm.Walk(5);
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true
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}
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pub fn SaveRegister(vm: &mut Machine) -> bool {
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let addr = vm.ReadWord(None);
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let reg = vm.ReadByte(None);
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let val = vm.registry.Get(reg);
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let (addr, reg) = Payload::GetAddressRegister(vm);
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vm.WriteWord(Some(addr), val);
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let data = vm.registry.Get(reg);
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vm.WriteWord(Some(addr), data);
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vm.Walk(5);
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true
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@ -33,131 +34,106 @@ pub fn Move(_vm: &mut Machine) -> bool {
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}
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pub fn Add(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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vm.registry.Set(reg, (op1 + op2).to_be_bytes());
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vm.Walk(3);
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true
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let payload = Payload::GetThreeRegisters(vm);
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_Add(vm, payload)
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}
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pub fn AddAssign(vm: &mut Machine) -> bool {
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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let payload = Payload::GetTwoRegisters(vm);
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_Add(vm, (payload.0, payload.0, payload.1))
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}
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vm.registry.Set(reg1, (op1 + op2).to_be_bytes());
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vm.Walk(2);
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#[inline]
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fn _Add(vm: &mut Machine, payload: ThreeRegisters) -> bool {
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let a = u32::from_be_bytes(vm.registry.Get(payload.1));
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let b = u32::from_be_bytes(vm.registry.Get(payload.2));
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vm.registry.Set(payload.0, (a + b).to_be_bytes());
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vm.Walk(3);
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true
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}
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pub fn Subtract(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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vm.registry.Set(reg, (op1 - op2).to_be_bytes());
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vm.Walk(3);
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true
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let payload = Payload::GetThreeRegisters(vm);
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_Subtract(vm, payload)
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}
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pub fn SubtractAssign(vm: &mut Machine) -> bool {
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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let payload = Payload::GetTwoRegisters(vm);
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_Subtract(vm, (payload.0, payload.0, payload.1))
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}
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vm.registry.Set(reg1, (op1 - op2).to_be_bytes());
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vm.Walk(2);
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#[inline]
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fn _Subtract(vm: &mut Machine, payload: ThreeRegisters) -> bool {
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let a = u32::from_be_bytes(vm.registry.Get(payload.1));
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let b = u32::from_be_bytes(vm.registry.Get(payload.2));
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vm.registry.Set(payload.0, (a - b).to_be_bytes());
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vm.Walk(3);
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true
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}
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pub fn Multiply(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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vm.registry.Set(reg, (op1 * op2).to_be_bytes());
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vm.Walk(3);
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true
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let payload = Payload::GetThreeRegisters(vm);
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_Multiply(vm, payload)
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}
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pub fn MultiplyAssign(vm: &mut Machine) -> bool {
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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let payload = Payload::GetTwoRegisters(vm);
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_Multiply(vm, (payload.0, payload.0, payload.1))
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}
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vm.registry.Set(reg1, (op1 * op2).to_be_bytes());
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vm.Walk(2);
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#[inline]
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fn _Multiply(vm: &mut Machine, payload: ThreeRegisters) -> bool {
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let a = u32::from_be_bytes(vm.registry.Get(payload.1));
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let b = u32::from_be_bytes(vm.registry.Get(payload.2));
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vm.registry.Set(payload.0, (a * b).to_be_bytes());
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vm.Walk(3);
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true
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}
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pub fn Divide(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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vm.registry.Set(reg, (op1 / op2).to_be_bytes());
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vm.Walk(3);
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true
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let payload = Payload::GetThreeRegisters(vm);
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_Divide(vm, payload)
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}
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pub fn DivideAssign(vm: &mut Machine) -> bool {
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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let payload = Payload::GetTwoRegisters(vm);
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_Divide(vm, (payload.0, payload.0, payload.1))
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}
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vm.registry.Set(reg1, (op1 / op2).to_be_bytes());
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vm.Walk(2);
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#[inline]
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fn _Divide(vm: &mut Machine, payload: ThreeRegisters) -> bool {
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let a = u32::from_be_bytes(vm.registry.Get(payload.1));
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let b = u32::from_be_bytes(vm.registry.Get(payload.2));
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vm.registry.Set(payload.0, (a * b).to_be_bytes());
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vm.Walk(3);
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true
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}
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pub fn Remainder(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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vm.registry.Set(reg, (op1 % op2).to_be_bytes());
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vm.Walk(3);
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true
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let payload = Payload::GetThreeRegisters(vm);
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_Remainder(vm, payload)
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}
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pub fn RemainderAssign(vm: &mut Machine) -> bool {
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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let payload = Payload::GetTwoRegisters(vm);
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_Remainder(vm, (payload.0, payload.0, payload.1))
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}
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vm.registry.Set(reg1, (op1 % op2).to_be_bytes());
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vm.Walk(2);
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#[inline]
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fn _Remainder(vm: &mut Machine, payload: ThreeRegisters) -> bool {
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let a = u32::from_be_bytes(vm.registry.Get(payload.1));
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let b = u32::from_be_bytes(vm.registry.Get(payload.2));
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vm.registry.Set(payload.0, (a * b).to_be_bytes());
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vm.Walk(3);
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true
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}
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@ -168,216 +144,186 @@ pub fn Neg(_vm: &mut Machine) -> bool {
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}
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pub fn And(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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vm.registry.Set(reg, (op1 & op2).to_be_bytes());
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vm.Walk(3);
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true
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let payload = Payload::GetThreeRegisters(vm);
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_And(vm, payload)
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}
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pub fn AndAssign(vm: &mut Machine) -> bool {
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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let payload = Payload::GetTwoRegisters(vm);
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_And(vm, (payload.0, payload.0, payload.1))
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}
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vm.registry.Set(reg1, (op1 & op2).to_be_bytes());
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vm.Walk(2);
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#[inline]
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fn _And(vm: &mut Machine, payload: ThreeRegisters) -> bool {
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let a = u32::from_be_bytes(vm.registry.Get(payload.1));
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let b = u32::from_be_bytes(vm.registry.Get(payload.2));
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vm.registry.Set(payload.0, (a & b).to_be_bytes());
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vm.Walk(3);
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true
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}
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pub fn Or(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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vm.registry.Set(reg, (op1 | op2).to_be_bytes());
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vm.Walk(3);
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true
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let payload = Payload::GetThreeRegisters(vm);
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_Or(vm, payload)
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}
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pub fn OrAssign(vm: &mut Machine) -> bool {
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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let payload = Payload::GetTwoRegisters(vm);
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_Or(vm, (payload.0, payload.0, payload.1))
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}
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vm.registry.Set(reg1, (op1 | op2).to_be_bytes());
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vm.Walk(2);
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#[inline]
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fn _Or(vm: &mut Machine, payload: ThreeRegisters) -> bool {
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let a = u32::from_be_bytes(vm.registry.Get(payload.1));
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let b = u32::from_be_bytes(vm.registry.Get(payload.2));
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vm.registry.Set(payload.0, (a | b).to_be_bytes());
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vm.Walk(3);
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true
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}
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pub fn Xor(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let payload = Payload::GetThreeRegisters(vm);
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_Xor(vm, payload)
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}
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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pub fn XorAssign(vm: &mut Machine) -> bool {
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let payload = Payload::GetTwoRegisters(vm);
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_Xor(vm, (payload.0, payload.0, payload.1))
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}
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vm.registry.Set(reg, (op1 ^ op2).to_be_bytes());
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#[inline]
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fn _Xor(vm: &mut Machine, payload: ThreeRegisters) -> bool {
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let a = u32::from_be_bytes(vm.registry.Get(payload.1));
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let b = u32::from_be_bytes(vm.registry.Get(payload.2));
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vm.registry.Set(payload.0, (a ^ b).to_be_bytes());
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vm.Walk(3);
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true
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}
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pub fn XorAssign(vm: &mut Machine) -> bool {
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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vm.registry.Set(reg1, (op1 ^ op2).to_be_bytes());
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vm.Walk(2);
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true
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}
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pub fn Not(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let op = u32::from_be_bytes(vm.registry.Get(reg));
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let r0 = Payload::GetRegister(vm);
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vm.registry.Set(reg, (!op).to_be_bytes());
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let a = u32::from_be_bytes(vm.registry.Get(r0));
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vm.registry.Set(r0, (!a).to_be_bytes());
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vm.Walk(2);
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true
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}
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pub fn ShiftLeft(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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vm.registry.Set(reg, (op1 << 1).to_be_bytes());
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vm.Walk(3);
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true
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let payload = Payload::GetTwoRegisters(vm);
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_ShiftLeft(vm, payload)
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}
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pub fn ShiftLeftAssign(vm: &mut Machine) -> bool {
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let payload = Payload::GetRegister(vm);
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_ShiftLeft(vm, (payload, payload))
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}
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vm.registry.Set(reg1, (op1 << 1).to_be_bytes());
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vm.Walk(2);
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#[inline]
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fn _ShiftLeft(vm: &mut Machine, payload: TwoRegisters) -> bool {
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let a = u32::from_be_bytes(vm.registry.Get(payload.1));
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vm.registry.Set(payload.0, (a << 1).to_be_bytes());
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vm.Walk(3);
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true
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}
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pub fn ShiftRight(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let payload = Payload::GetTwoRegisters(vm);
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_ShiftRight(vm, payload)
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}
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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pub fn ShiftRightAssign(vm: &mut Machine) -> bool {
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let payload = Payload::GetRegister(vm);
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_ShiftRight(vm, (payload, payload))
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}
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vm.registry.Set(reg, (op1 >> 1).to_be_bytes());
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#[inline]
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fn _ShiftRight(vm: &mut Machine, payload: TwoRegisters) -> bool {
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let a = u32::from_be_bytes(vm.registry.Get(payload.1));
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vm.registry.Set(payload.0, (a >> 1).to_be_bytes());
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vm.Walk(3);
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true
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}
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pub fn ShiftRightAssign(vm: &mut Machine) -> bool {
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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vm.registry.Set(reg1, (op1 >> 1).to_be_bytes());
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vm.Walk(2);
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true
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}
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pub fn Equals(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
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let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
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let reg1 = vm.ReadByte(None);
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let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
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let reg2 = vm.ReadByte(None);
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let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
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let a = u32::from_be_bytes(vm.registry.Get(r1));
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let b = u32::from_be_bytes(vm.registry.Get(r2));
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vm.registry.Set(reg, ((op1 == op2) as u32).to_be_bytes());
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vm.registry.Set(r0, ((a == b) as u32).to_be_bytes());
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vm.Walk(3);
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true
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}
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pub fn NotEquals(vm: &mut Machine) -> bool {
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let reg = vm.ReadByte(None);
|
||||
let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
|
||||
|
||||
let reg1 = vm.ReadByte(None);
|
||||
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
|
||||
let reg2 = vm.ReadByte(None);
|
||||
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
|
||||
let a = u32::from_be_bytes(vm.registry.Get(r1));
|
||||
let b = u32::from_be_bytes(vm.registry.Get(r2));
|
||||
|
||||
vm.registry.Set(reg, ((op1 != op2) as u32).to_be_bytes());
|
||||
vm.registry.Set(r0, ((a != b) as u32).to_be_bytes());
|
||||
vm.Walk(3);
|
||||
|
||||
true
|
||||
}
|
||||
|
||||
pub fn LessThan(vm: &mut Machine) -> bool {
|
||||
let reg = vm.ReadByte(None);
|
||||
let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
|
||||
|
||||
let reg1 = vm.ReadByte(None);
|
||||
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
|
||||
let reg2 = vm.ReadByte(None);
|
||||
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
|
||||
let a = u32::from_be_bytes(vm.registry.Get(r1));
|
||||
let b = u32::from_be_bytes(vm.registry.Get(r2));
|
||||
|
||||
vm.registry.Set(reg, ((op1 < op2) as u32).to_be_bytes());
|
||||
vm.registry.Set(r0, ((a < b) as u32).to_be_bytes());
|
||||
vm.Walk(3);
|
||||
|
||||
true
|
||||
}
|
||||
|
||||
pub fn LessEquals(vm: &mut Machine) -> bool {
|
||||
let reg = vm.ReadByte(None);
|
||||
let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
|
||||
|
||||
let reg1 = vm.ReadByte(None);
|
||||
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
|
||||
let reg2 = vm.ReadByte(None);
|
||||
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
|
||||
let a = u32::from_be_bytes(vm.registry.Get(r1));
|
||||
let b = u32::from_be_bytes(vm.registry.Get(r2));
|
||||
|
||||
vm.registry.Set(reg, ((op1 <= op2) as u32).to_be_bytes());
|
||||
vm.registry.Set(r0, ((a <= b) as u32).to_be_bytes());
|
||||
vm.Walk(3);
|
||||
|
||||
true
|
||||
}
|
||||
|
||||
pub fn GreaterThan(vm: &mut Machine) -> bool {
|
||||
let reg = vm.ReadByte(None);
|
||||
let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
|
||||
|
||||
let reg1 = vm.ReadByte(None);
|
||||
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
|
||||
let reg2 = vm.ReadByte(None);
|
||||
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
|
||||
let a = u32::from_be_bytes(vm.registry.Get(r1));
|
||||
let b = u32::from_be_bytes(vm.registry.Get(r2));
|
||||
|
||||
vm.registry.Set(reg, ((op1 > op2) as u32).to_be_bytes());
|
||||
vm.registry.Set(r0, ((a > b) as u32).to_be_bytes());
|
||||
vm.Walk(3);
|
||||
|
||||
true
|
||||
}
|
||||
|
||||
pub fn GreaterEquals(vm: &mut Machine) -> bool {
|
||||
let reg = vm.ReadByte(None);
|
||||
let (r0, r1, r2) = Payload::GetThreeRegisters(vm);
|
||||
|
||||
let reg1 = vm.ReadByte(None);
|
||||
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
|
||||
let reg2 = vm.ReadByte(None);
|
||||
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
|
||||
let a = u32::from_be_bytes(vm.registry.Get(r1));
|
||||
let b = u32::from_be_bytes(vm.registry.Get(r2));
|
||||
|
||||
vm.registry.Set(reg, ((op1 >= op2) as u32).to_be_bytes());
|
||||
vm.registry.Set(r0, ((a >= b) as u32).to_be_bytes());
|
||||
vm.Walk(3);
|
||||
|
||||
true
|
||||
|
||||
33
Source/Payload.rs
Normal file
33
Source/Payload.rs
Normal file
@ -0,0 +1,33 @@
|
||||
use crate::Machine;
|
||||
use crate::Types::{Byte, Word};
|
||||
|
||||
pub type RegisterAddress = (Byte, Word);
|
||||
pub type AddressRegister = (Word, Byte);
|
||||
pub type Register = Byte;
|
||||
pub type TwoRegisters = (Byte, Byte);
|
||||
pub type ThreeRegisters = (Byte, Byte, Byte);
|
||||
|
||||
#[inline]
|
||||
pub fn GetRegisterAddress(vm: &mut Machine) -> RegisterAddress {
|
||||
(vm.ReadByte(None), vm.ReadWord(None))
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn GetAddressRegister(vm: &mut Machine) -> AddressRegister {
|
||||
(vm.ReadWord(None), vm.ReadByte(None))
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn GetRegister(vm: &mut Machine) -> Register {
|
||||
vm.ReadByte(None)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn GetTwoRegisters(vm: &mut Machine) -> TwoRegisters {
|
||||
(vm.ReadByte(None), vm.ReadByte(None))
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn GetThreeRegisters(vm: &mut Machine) -> ThreeRegisters {
|
||||
(vm.ReadByte(None), vm.ReadByte(None), vm.ReadByte(None))
|
||||
}
|
||||
@ -1,5 +1,2 @@
|
||||
/// Canonical byte type.
|
||||
pub type Byte = u8;
|
||||
|
||||
/// Canonical data and address type.
|
||||
pub type Word = [u8; 4];
|
||||
pub type Word = [Byte; 4];
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
mod Instructions;
|
||||
|
||||
pub mod Operations;
|
||||
pub mod Payload;
|
||||
pub mod Types;
|
||||
|
||||
#[path = "Limits.rs"]
|
||||
|
||||
Reference in New Issue
Block a user