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Werner
2021-11-19 17:55:40 -03:00
parent 8b7501fb91
commit ae70b9db3d
11 changed files with 409 additions and 324 deletions
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372
Source/Instructions.rs
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@ -1,34 +1,28 @@
use crate::Machine;
pub fn Nothing(vm: &mut Machine) -> bool {
vm.WalkAddress(1);
vm.Next();
true
}
pub fn LoadRegister(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let addr = vm.ReadWord(None);
let val = vm.ReadWord(Some(addr));
let reg = vm.GetMemory(pc + 1);
let addr = vm.GetMemory(pc + 2);
let val = vm.GetMemory(addr);
vm.SetRegister(reg, val);
vm.WalkAddress(3);
vm.registry.Set(reg, val);
vm.Walk(5);
true
}
pub fn SaveRegister(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let addr = vm.ReadWord(None);
let reg = vm.ReadByte(None);
let val = vm.registry.Get(reg);
let addr = vm.GetMemory(pc + 1);
let reg = vm.GetMemory(pc + 2);
let val = vm.GetRegister(reg);
vm.SetMemory(addr, val);
vm.WalkAddress(3);
vm.WriteWord(Some(addr), val);
vm.Walk(5);
true
}
@ -39,136 +33,131 @@ pub fn Move(_vm: &mut Machine) -> bool {
}
pub fn Add(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, op1 + op2);
vm.WalkAddress(4);
vm.registry.Set(reg, (op1 + op2).to_be_bytes());
vm.Walk(3);
true
}
pub fn AddAssign(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(reg);
let op2 = vm.GetRegister(vm.GetMemory(pc + 2));
vm.SetRegister(reg, op1 + op2);
vm.WalkAddress(3);
vm.registry.Set(reg1, (op1 + op2).to_be_bytes());
vm.Walk(2);
true
}
pub fn Subtract(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, op1 - op2);
vm.WalkAddress(4);
vm.registry.Set(reg, (op1 - op2).to_be_bytes());
vm.Walk(3);
true
}
pub fn SubtractAssign(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(reg);
let op2 = vm.GetRegister(vm.GetMemory(pc + 2));
vm.SetRegister(reg, op1 - op2);
vm.WalkAddress(3);
vm.registry.Set(reg1, (op1 - op2).to_be_bytes());
vm.Walk(2);
true
}
pub fn Multiply(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, op1 * op2);
vm.WalkAddress(4);
vm.registry.Set(reg, (op1 * op2).to_be_bytes());
vm.Walk(3);
true
}
pub fn MultiplyAssign(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(reg);
let op2 = vm.GetRegister(vm.GetMemory(pc + 2));
vm.SetRegister(reg, op1 * op2);
vm.WalkAddress(3);
vm.registry.Set(reg1, (op1 * op2).to_be_bytes());
vm.Walk(2);
true
}
pub fn Divide(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, op1 / op2);
vm.WalkAddress(4);
vm.registry.Set(reg, (op1 / op2).to_be_bytes());
vm.Walk(3);
true
}
pub fn DivideAssign(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(reg);
let op2 = vm.GetRegister(vm.GetMemory(pc + 2));
vm.SetRegister(reg, op1 / op2);
vm.WalkAddress(3);
vm.registry.Set(reg1, (op1 / op2).to_be_bytes());
vm.Walk(2);
true
}
pub fn Remainder(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, op1 % op2);
vm.WalkAddress(4);
vm.registry.Set(reg, (op1 % op2).to_be_bytes());
vm.Walk(3);
true
}
pub fn RemainderAssign(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(reg);
let op2 = vm.GetRegister(vm.GetMemory(pc + 2));
vm.SetRegister(reg, op1 % op2);
vm.WalkAddress(3);
vm.registry.Set(reg1, (op1 % op2).to_be_bytes());
vm.Walk(2);
true
}
@ -179,220 +168,217 @@ pub fn Neg(_vm: &mut Machine) -> bool {
}
pub fn And(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, op1 & op2);
vm.WalkAddress(4);
vm.registry.Set(reg, (op1 & op2).to_be_bytes());
vm.Walk(3);
true
}
pub fn AndAssign(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(reg);
let op2 = vm.GetRegister(vm.GetMemory(pc + 2));
vm.SetRegister(reg, op1 & op2);
vm.WalkAddress(3);
vm.registry.Set(reg1, (op1 & op2).to_be_bytes());
vm.Walk(2);
true
}
pub fn Or(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, op1 | op2);
vm.WalkAddress(4);
vm.registry.Set(reg, (op1 | op2).to_be_bytes());
vm.Walk(3);
true
}
pub fn OrAssign(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(reg);
let op2 = vm.GetRegister(vm.GetMemory(pc + 2));
vm.SetRegister(reg, op1 | op2);
vm.WalkAddress(3);
vm.registry.Set(reg1, (op1 | op2).to_be_bytes());
vm.Walk(2);
true
}
pub fn Xor(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, op1 ^ op2);
vm.WalkAddress(4);
vm.registry.Set(reg, (op1 ^ op2).to_be_bytes());
vm.Walk(3);
true
}
pub fn XorAssign(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(reg);
let op2 = vm.GetRegister(vm.GetMemory(pc + 2));
vm.SetRegister(reg, op1 ^ op2);
vm.WalkAddress(3);
vm.registry.Set(reg1, (op1 ^ op2).to_be_bytes());
vm.Walk(2);
true
}
pub fn Not(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let op = u32::from_be_bytes(vm.registry.Get(reg));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
vm.SetRegister(reg, !op1);
vm.WalkAddress(3);
vm.registry.Set(reg, (!op).to_be_bytes());
vm.Walk(2);
true
}
pub fn ShiftLeft(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
vm.SetRegister(reg, op1 << 1);
vm.WalkAddress(4);
vm.registry.Set(reg, (op1 << 1).to_be_bytes());
vm.Walk(3);
true
}
pub fn ShiftLeftAssign(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(reg);
vm.SetRegister(reg, op1 << 1);
vm.WalkAddress(2);
vm.registry.Set(reg1, (op1 << 1).to_be_bytes());
vm.Walk(2);
true
}
pub fn ShiftRight(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
vm.SetRegister(reg, op1 >> 1);
vm.WalkAddress(4);
vm.registry.Set(reg, (op1 >> 1).to_be_bytes());
vm.Walk(3);
true
}
pub fn ShiftRightAssign(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(reg);
vm.SetRegister(reg, op1 >> 1);
vm.WalkAddress(2);
vm.registry.Set(reg1, (op1 >> 1).to_be_bytes());
vm.Walk(2);
true
}
pub fn Equals(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, (op1 == op2) as u8);
vm.WalkAddress(4);
vm.registry.Set(reg, ((op1 == op2) as u32).to_be_bytes());
vm.Walk(3);
true
}
pub fn NotEquals(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, (op1 != op2) as u8);
vm.WalkAddress(4);
vm.registry.Set(reg, ((op1 != op2) as u32).to_be_bytes());
vm.Walk(3);
true
}
pub fn LessThan(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, (op1 < op2) as u8);
vm.WalkAddress(4);
vm.registry.Set(reg, ((op1 < op2) as u32).to_be_bytes());
vm.Walk(3);
true
}
pub fn LessEquals(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, (op1 <= op2) as u8);
vm.WalkAddress(4);
vm.registry.Set(reg, ((op1 <= op2) as u32).to_be_bytes());
vm.Walk(3);
true
}
pub fn GreaterThan(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, (op1 > op2) as u8);
vm.WalkAddress(4);
vm.registry.Set(reg, ((op1 > op2) as u32).to_be_bytes());
vm.Walk(3);
true
}
pub fn GreaterEquals(vm: &mut Machine) -> bool {
let pc = vm.GetAddress();
let reg = vm.ReadByte(None);
let reg = vm.GetMemory(pc + 1);
let op1 = vm.GetRegister(vm.GetMemory(pc + 2));
let op2 = vm.GetRegister(vm.GetMemory(pc + 3));
let reg1 = vm.ReadByte(None);
let op1 = u32::from_be_bytes(vm.registry.Get(reg1));
let reg2 = vm.ReadByte(None);
let op2 = u32::from_be_bytes(vm.registry.Get(reg2));
vm.SetRegister(reg, (op1 >= op2) as u8);
vm.WalkAddress(4);
vm.registry.Set(reg, ((op1 >= op2) as u32).to_be_bytes());
vm.Walk(3);
true
}