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Werner
2021-12-10 13:49:16 -03:00
parent 79cfa207c4
commit 4cd8620325
10 changed files with 261 additions and 433 deletions
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26
Source/Machine.rs
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@ -53,35 +53,21 @@ impl Machine {
self.mp = self.pc + 1;
running = match opcode {
NOP => Nothing(&mut self),
LDR => LoadRegister(&mut self),
STR => StoreRegister(&mut self),
LDA_W => LoadRegister(&mut self),
STA_W => StoreRegister(&mut self),
INC => IncrementRegister(&mut self),
DEC => DecrementRegister(&mut self),
ADD => Add(&mut self),
ADD_ASSIGN => AddAssign(&mut self),
SUB => Subtract(&mut self),
SUB_ASSIGN => SubtractAssign(&mut self),
MUL => Multiply(&mut self),
MUL_ASSIGN => MultiplyAssign(&mut self),
DIV => Divide(&mut self),
DIV_ASSIGN => DivideAssign(&mut self),
REM => Remainder(&mut self),
REM_ASSIGN => RemainderAssign(&mut self),
//NEG
NEG => Neg(&mut self),
AND => And(&mut self),
AND_ASSIGN => AndAssign(&mut self),
OR => Or(&mut self),
OR_ASSIGN => OrAssign(&mut self),
XOR => Xor(&mut self),
XOR_ASSIGN => XorAssign(&mut self),
NOT => Not(&mut self),
NAND => Nand(&mut self),
NOR => Nor(&mut self),
XNOR => Xnor(&mut self),
SHL => ShiftLeft(&mut self),
SHL_ASSIGN => ShiftLeftAssign(&mut self),
SHR => ShiftRight(&mut self),
SHR_ASSIGN => ShiftRightAssign(&mut self),
EQ => Equals(&mut self),
NEQ => NotEquals(&mut self),
LT => LessThan(&mut self),
LE => LessEquals(&mut self),
GT => GreaterThan(&mut self),